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Verilog Styles for Synthesis of Digital Systems


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Table of Contents

(NOTE: Most chapters begin with Introduction and end with Conclusion, Exercises, and References.)

1. Introduction.


2. Basic Language Constructs.

Preliminaries. Datatypes. Modules.

3. Structural and Behavioral Specification.

Basic Gates. Modeling Levels. Writing Styles. Synthesizable Operations. Continuous Assignments.

4. Simulation.

Types of Simulators. Using the VCS Simulator. Testbenches. Debugging.

5. Procedural Specification.

The Always Block. Functions and Tasks. Blocking and Non-Blocking Assignments. Control Constructs. Synthesis of Conditional Constructs. Example: Combinational Modules. Flipflops versus Latches. Memory.

6. Design Approaches for Single Modules.

Basic Design Methodology. The Specification. Structuring the Design. Design Example 1-A Simple Down Counter. Example 2-Unsigned Parallel-Serial Multiplier. An Alternative Approach to Specifying Flipflops. Common Problems and Fixes. Debugging Strategies.

7. Validation of Single Modules.

Sources of Verification Vectors. Verification Testbench Coding Approaches. Post-Synthesis Verification. Formal Verification. System-Level Verification.

8. Finite State Machine Styles.

Synthesis of State Machines. Example Specifications.

9. Control-Point Writing Style.

Instantiation of Parameterized Modules. Control-Point Style. Using Vendor's Components.

10. Managing Complexity-Large Designs.

Steps in High-Level Design. Design Partitioning. Controller Design Styles. Example of Explicit Style-Motion Estimator. Example of Implicit Style-Cache Store. Another Implicit Style Example: MIPS200.

11. Improving Timing, Area, and Power.

Timing Issues in Design. Low Power Design. Area Issues in Design.

12. Design Compilation.

Running Example: Alarm Clock. Setting Up. Invoking Synthesis. The Log File.

13. Synthesis to Standard Cells.

Synthesis Flow.

14. Synthesis to FPGA.

FPGA as a Target Technology. Using the Altera Tools. Using the Xilinx Tools. Generating Memory Arrays. Using Embedded Arrays as ROM. FPGA Reports. Gate-Level Simulation.

15. Gate Level Simulation and Testing.

Ad-Hoc Test Techniques. Scan Insertion in Synthesis. Built-in Self-Test.

16. Alternative Writing Styles.

Behavioral Compiler Styles. Self-Timed Style. Encapsulated Style. Future HDL Development.

17. Mixed Technology Design.

Digital/Analog. Hardware/Software. A Small Example.

Appendix A: Verilog Examples.

Combinational Logic Structures. Sequential Logic Structures.

Appendix B:


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