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Preface 1 Fundamental Concepts 2 Scalar Data Types and Operations 3 Sequential Statements 4 Composite Data Types and Operations 5 Basic Modeling Constructs 6 Subprograms 7 Packages and Use Clauses 8 Aliases 9 Resolved Signals 10 Generics 11 Components 12 Generate Statements 13 Design for Synthesis 14 Case Study: System Design using the Gumnut Core A Standard Packages B VHDL Syntax C Differences Among VHDL Versions D Answers to Exercises References Index
Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.