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Co-Synthesis of Hardware and Software for Digital Embedded Systems

Co-Synthesis of Hardware and Software for Digital Embedded Systems, with a Foreword written by Giovanni De Micheli, presents techniques that are useful in building complex embedded systems. These techniques provide a competitive advantage over purely hardware or software implementations of time-constrained embedded systems. Recent advances in chip-level synthesis have made it possible to synthesize application-specific circuits under strict timing constraints. This work advances the state of the art by formulating the problem of system synthesis using both application-specific as well as reprogrammable components, such as off-the-shelf processors. Timing constraints are used to determine what part of the system functionality must be delegated to dedicated application-specific hardware while the rest is delegated to software that runs on the processor. This co-synthesis of hardware and software from behavioral specifications makes it possible to realize real-time embedded systems using off-the-shelf parts and a relatively small amount of application-specific circuitry that can be mapped to semi-custom VLSI such as gate arrays. The ability to perform detailed analysis of timing performance provides the opportunity of improving the system definition by creating better phototypes. Co-Synthesis of Hardware and Software for Digital Embedded Systems is of interest to CAD researchers and developers who want to branch off into the expanding field of hardware/software co-design, as well as to digital system designers who are interested in the present power and limitations of CAD techniques and their likely evolution.
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Table of Contents

Foreword. Preface. 1. Introduction. 2. Related Work. 3. System Modeling. 4. Constraint Analysis. 5. Software and Runtime Environment. 6. System Partitioning. 7. System Implementation. 8. Examples and Results. 9. Summary, Conclusions, and Future Work. Bibliography. References. A: A Note on Hardware. B: Bilogic Graphs. C: Processor Characterization in VULCAN. D: Runtime Scheduler Routines. Index.

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