Circuit Design with VHDL


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About the Author

Volnei A. Pedroni is Professor Emeritus in the Electronics Engineering Department at Brazil's Federal University of Technology, UTFPR, and a regular Visiting Professor of Electrical Engineering at the California Institute of Technology. Dr. Pedroni's MSc and PhD degrees are both from Caltech. He is the author of Finite State Machines in Hardware- Theory and Design (with VHDL and SystemVerilog) (MIT Press).

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