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Advanced FPGA Design

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Table of Contents

Preface. Acknowledgments. Chapter 1. Architecting Speed. High Throughput. Low Latency. Timing. Add Register Layers. Parallel Structures. Flatten Logic Structures. Register Balancing. Reorder Paths. Summary of Key Points. Chapter 2. Architecting Area. Rolling-up the Pipeline. Control Based Logic Reuse. Resource Sharing. Impact of Reset on Area. Resources without Reset. Resources without Set. Resources without Asynchronous Reset. Resetting RAM. Utilizing Set/Reset Flip-Flop Pins. Summary of Key Points. Chapter 3. Architecting Power. Clock Gating. Clock Skew. Managing Skew. Gated Domains. Input Control. Reducing the Voltage Supply. Dual-Edge Triggered Flip-Flops. Modifying Terminations . Summary of Key Points . Chapter 4. Example Design: The Advanced Encryption Standard. AES Architectures. Compact Architecture. Partially Pipelined Architecture. Fully Pipelined Architecture. Performance versus Area. Other Optimizations. Chapter 5. High Level Design. Abstract Design Techniques. Graphical State Machines. DSP Design. Software/Hardware Co-Design. Summary of Key Points. Chapter 6. Clock Domains. Crossing Clock Domains. Metastability. Solution 1: Phase Control. Solution 2: Double-flopping. Solution 3: FIFO Structure. Partitioning Synchronizer Blocks. Gated Clocks in ASIC Prototypes. Clocks Module. Gating Removal. Summary of Key Points. Chapter 7. Example Design: I2S versus SPDIF. I2S. Protocol. Hardware Architecture. Analysis. SPDIF. Protocol. Hardware Architecture. Analysis. Chapter 8. Implementing Math Functions. Hardware Division. Multiply and Shift. Iterative Division. The Goldschmidt Method. Taylor and Maclaurin Series Expansion. The CORDIC Algorithm. Summary of Key Points. Chapter 9. Example Design: Floating Point Unit. Floating Point Formats. Pipelined Architecture. Verilog Implementation. Resources and Performance. Chapter 10. Reset Circuits. Asynchronous versus Synchronous. Problems with Fully Asynchronous Resets. Fully Synchronized Resets. Asynchronous Assertion, Synchronous Deassertion. Mixing Reset Types. Non-Resetable Flip-Flops. Internally Generated Resets. Multiple Clock Domains. Summary of Key Points. Chapter 11. Advanced Simulation. Testbench Architecture. Testbench Components. Testbench Flow. Main Thread. Clocks and Resets. Testcases. System Stimulus. Matlab. Bus-functional Models. Code Coverage. Gate Level Simulations. Toggle Coverage. Run-Time Traps. Timescale. Glitch Rejection. Combinatorial Delay Modeling. Summary of Key Points. Chapter 12. Coding for Synthesis. Decision Trees. Priority versus Parallel. Full Conditions. Multiple Control Branches. Traps. Blocking versus Nonblocking. For Loops. Combinatorial Loops. Inferred Latches. Functions. Design Organization. Partitioning. Datapath versus Control. Clock and Reset Structures. Multiple Instantiations. Parameterization. Definitions. Parameters. Parameters in Verilog-2001. Summary of Key Points. Chapter 13. Example Design: The Secure Hash Algorithm. SHA-1 Architecture. Implementation Results. Chapter 14. Synthesis Optimization. Speed versus Area. Resource Sharing. Pipelining, Retiming, and Register Balancing. The Effect of Reset on Register Balancing. Resynchronization Registers. FSM Compilation. Removal of Unreachable States. Black Boxes. Physical Synthesis. Forward versus Back-Annotation. Graph Based Physical Synthesis. Summary of Key Points. Chapter 15. Floorplanning. Design Partitioning. Critical Path Floorplanning. Floorplanning Dangers. Optimal Floorplanning. Data Path. High Fan-Out. Device Structure. Reusability. Reducing Power Dissipation. Summary of Key Points. Chapter 16. Place and Route Optimization. Optimal Constraints. Relationship between Placement and Routing. Logic Replication. Optimization across Hierarchy. I/O Registers. Pack Factor. Mapping Logic into RAM. Register Ordering. Placement Seed. Guided Place and Route. Summary of Key Points. Chapter 17. Example Design: Microprocessor. SRC Architecture. Synthesis Optimizations. Speed versus Area. Pipelining. Physical Synthesis. Floorplan Optimizations. Partitioned Floorplan. Critical Path Floorplan: Abstraction 1. Critical Path Floorplan: Abstraction 2. Chapter 18. Static Timing Analysis. Standard Analysis. Latches. Asynchronous Circuits. Combinatorial Feedback. Event Driven Clocks. Summary of Key Points. Chapter 19. PCB Issues. Power Supply. Supply Requirements. Regulation. Decoupling Capacitors. Concept. Calculating Values. Capacitor Placement. Power Planes. Modeling Signal Reflections. Spice Simulations. Configuration. Debug. Code Modifications. FPGA Editor. Placement. Properties. Routing. ChipScope. Identify. Summary of Key Points. Appendix A. Appendix B. Bibliography. Index.

About the Author

Steve Kilts is a cofounder and principal engineer at Spectrum Design Solutions, an engineering consulting firm based out of Minneapolis, Minnesota ( Mr. Kilts and his team at Spectrum have successfully completed projects for clients ranging from Fortune 100 companies to small start-ups. His FPGA design experience is extensive and includes applications in audio, DSP, high-speed computing and bus architectures, IC testers, industrial automation and control, embedded microprocessors, PCI, medical system design, commercial aviation, and ASIC prototyping. Mr. Kilts has many years of experience making performance trade-offs for FPGA designs targeting high speed, area reduction, and low power. He holds a master of science degree in electrical engineering from the University of Minnesota.


"Advanced FPGA Design is an excellent and concise reference book that is suitable for engineers already familiar with the fundamentals of FPGA design. (IEEE Signal Processing Magazine, November 2008)

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